
`ifndef PLL_DEF
`define PLL_DEF(a,b,c)
`endif

`ifndef PLL_RV_DEF
`define PLL_RV_DEF
`endif

//12MHz
`define HSE_VALUE 32'd12_000_000

module led (
    test_pin,
    PIN_HSE,
    PIN_HSI,
    led_pin,
);

    output wire[31:0] test_pin;
    input wire PIN_HSE;
    input wire PIN_HSI;
    output wire led_pin;

    assign test_pin[0] = PIN_HSE;
    assign test_pin[1] = sys_gck;
    assign test_pin[2] = led_reg;
    assign led_pin = led_reg;
    reg led_reg = 1'b0;

    `PLL_DEF("12.0",8'd36,8'd37);

    //定义一个时钟
    def_clk _clk(sys_gck,clk_out);

    //时序逻辑
    reg [31:0] counter = 32'd0;
    assign test_pin[31:3] = counter[31-3:3-3];
    always @(posedge clk_out) begin
        //需要0.5s切换一次电平
        if({counter,1'b0}==`HSE_VALUE)begin
            led_reg <= !led_reg;
            counter <= 32'd0;
        end
        else
            counter <= counter + 32'd1;
    end

    alta_rv32 rv32(
        `PLL_RV_DEF
    );

endmodule